The present invention relates to a method for producing a semiconductor device and a semiconductor device, more particularly to a method for producing a semiconductor device by using a plasma doping method and a semiconductor device.
Reflecting the trend to fine structure and high integration of semiconductor devices in recent years, it is required to form shallowly a source/drain junction of a MOS transistor and an extension portion as a medium concentration portion of a source/drain formed by e.g. LDD (Lightly Doped Drain). With the change of design rules in the trend to fine structure of MOS transistors, if the source/drain junction including the extension portion is not shallowly formed, drawbacks such as a short-channel effect are likely to occur.
Heretofore, an ion implantation method has been used for the formation of a source/drain junction. However, the formation of a shallow source/drain junction by the ion implantation method has the following drawbacks. For the formation of a shallow source/drain diffusion layer junction by an ion implantation apparatus, it is required to implant ions with low energy. However, a high beam current is hardly obtained with low energy. This is mainly attributable to the fact that with the low energy, ion beams introduced from an ion source tend to diffuse and disperse until they reach a wafer. It takes a long time to obtain a predetermined implantation dose due to the less beam current, resulting in poor throughput.
Under such circumstances, a plasma doping method by which doping is feasible with high throughput even with low energy, attracts attentions. Especially with respect to a low energy doping of boron (B) which exhibits poor throughput by an ion implantation apparatus, studies have been intensively made.
With respect to the plasma doping, the following prior art documents are mentioned.
First, JP-A-8-45867 describes that to improve the ionization probability of phosphine gas, an ion shower with phosphine gas diluted with hydrogen gas and helium gas is used for the formation of source/drain regions.
Further, JP-A-7-142421 describes that plasma ion implantation of Ge and Si into a semiconductor substrate is conducted to induce preamorphized state, and then plasma ion implantation of P-type or N-type ions as impurities is conducted.
Moreover, JP-A-6-89904 describes that plasma ion implantation of trivalent or pentavalent impurities in plasma state diluted with hydrogen or helium, is conducted for formation of an impurity region.
As described above, documents concerning the gas composition for plasma doping and technics concerning source/drain regions are found in the prior art.
Problems of conventional plasma doping methods wherein B.sub.2 H.sub.6 is used as a main gas of dopant will be explained.
FIG. 14 is a cross-sectional schematic view of a device when doping is carried out on source/drain and a gate electrode of a surface channel type PMOS transistor by using B.sub.2 H.sub.6 as the main gas of dopant.
In FIG. 14, 51 is a semiconductor substrate, 52 is an oxide film for separation of elements formed on the semiconductor substrate 51 by a LOCOS method (Local Oxidation of Silicon), 53 is a gate oxide film formed on the semiconductor substrate 51, 54 is a gate electrode formed on the gate oxide film 53, 55 is source/drain regions, and 56 is an electron trap generated in the gate oxide film 53.
Then, with reference to the cross-sectional schematic view of a device as shown in FIG. 14, a production method will be explained.
First, an oxide film 52 for separation of elements is formed on a semiconductor substrate 51 by a LOCOS method. Then, a gate oxide film 53 is formed on the semiconductor substrate 51 by thermal oxidation, and an undoped-type polysilicon or an amorphous silicon is formed on the gate oxide film 53 by a CVD method. Then, through a resist process, patterning is conducted in the shape as shown in FIG. 14 by an anisotropic etching.
FIG. 14 shows the condition where a semiconductor substrate 51 is mounted on an electrode in a plasma doping apparatus which is not shown, and doping of impurities in plasma state is carried out on source/drain 55 and a gate electrode 54 of the semiconductor substrate 51. B.sub.2 H.sub.6 as a dopant is usually diluted to 20% or less with hydrogen or the like for use, since it is extremely unstable as a single substance. When plasma is generated by using B.sub.2 H.sub.6 diluted with hydrogen, ions such as B.sup.+, BH.sub.x.sup.+ (x=1 to 6), B.sub.2 H.sub.x.sup.+ (x=1 to 6), H.sub.3.sup.+, H.sub.2.sup.+ or H.sup.+ ions, or radicals such as H* (hereinafter * indicates to be a radical) are generated. However, the existence ratio of B+ in the plasma is low and the major part is hydrogen ions (H.sub.3.sup.+, H.sub.2.sup.+) or ions containing hydrogen (B.sub.2 H.sub.x.sup.+).
When 31 4 kV is applied to the electrode in the plasma doping apparatus which is not shown, to carry out the doping of B.sub.2 H.sub.x.sup.+ at a ratio of 1.times.10.sup.15 cm.sup.-2 at 4 keV, a large amount of H.sub.3.sup.+ exists in the plasma and accelerated by 4 keV to undergo doping into the semiconductor substrate 51. In this case, B.sub.2 H.sub.x.sup.+ does not pass through the gate electrode 54, but hydrogen passes beyond the gate electrode 54 and is doped into the gate oxide film 53 at a level of 1.times.10.sup.17 cm.sup.-3. The hydrogen causes an electron trap 56 in the gate oxide film 53. Then, the electron trap causes the drawback of deterioration of hot-carrier resistance.
Further, in another conventional plasma doping method, the main gas is BF.sub.3 gas as a dopant.
FIG. 15 is a schematic view illustrating the principle of the plasma doping when BF.sub.3 is used as the main gas. In FIG. 15, 57 is an electrode in the plasma doping apparatus, and 58 is a semiconductor substrate mounted on the electrode 57.
By applying a negative voltage to the electrode 57, positive ions in plasma state are attracted to the semiconductor substrate 58 and doped by an acceleration voltage. The electrons in the plasma move away from the semiconductor substrate 58. Usually, to prevent charging up, a negative pulse pattern voltage is applied to the electrode 57. Only during the negative voltage is applied, positive ions are implanted into the semiconductor substrate 58, and when the applied voltage becomes 0 or positive, the electrons are attracted to neutralize the charging up.
When the BF.sub.3 gas is used as the main gas, positive ions of all the types existing in the plasma, i.e. B.sup.+, BF.sup.+, BF.sub.2.sup.+ and F.sup.+, are doped at the same time into a wafer. However, the BF.sub.2.sup.+ ions having the highest existence ratio are widely used in an ion implantation method and cause no problem even if incorporated. Further, BF.sup.+ and F.sup.+ are considered to be less influential to the device, as well. Further, BF.sub.3 gas is not flammable unlike B.sub.2 H.sub.6, and accordingly, has a merit of easiness in handling from the viewpoint of safety.
However, as shown in FIG. 15, when the BF.sub.3 gas is used, fluorine radical F* formed by decomposition of the gas performs etching of the surface of the semiconductor substrate 58, i.e. together with the doping of the positive ions, the etching of the semiconductor substrate surface by the fluorine radical F* proceeds concomitantly, resulting in a drawback of poor controllability of doping profile.
Further, the boron once doped in the surface of the semiconductor substrate is etched, whereby a drawback of a poor doping efficiency is caused.
The above problems are described in, for example, "Anomalous behavior of shallow BF.sub.3 plasma immersion ion implantation", J. Vac. Sci. Technol. B12(2), Mar/Apr 1994, pp 956-961.
Here, prior art documents concerning plasma technologies using fluorine gas will be described.
As the prior art document concerning the plasma etching using fluorine gas, "LSI Process Engineering (2nd edition)" Ohm Co., pages 88-89, describes that if hydrogen is added to Freon during plasma etching, the formation of F* is prevented by the reaction of F* +H.fwdarw.HF, resulting in the reduction of etching rate of silicon.
Further, "Radical Kinetics in a Fluorocarbon Etching Plasma", Jpn. J. Appl. Phys. Vol. 32 (1993) pp. 3040-3044 describes that if plasma is generated by the addition of hydrogen gas to CF.sub.4 gas, a reaction of H+F.fwdarw.HF is induced, resulting in the reduction of F in the plasma.
Furthermore, "Formation of carbon fluoride film having a high heat resistance and a low dielectric constant by using a plasma CVD method", applied physics Vol. 65, No. 11, 1996, pp 1153-1157, describes that if hydrogen or C.sub.2 H.sub.2 is added to C.sub.4 F.sub.8 gas to generate plasma, gettering of F* by H* is likely to occur to reduce the etching with F*, resulting in increase of a film-formation rate.
As described above, prior art documents concerning the plasma etching by using fluorine gas are found in the prior art.
Then, in the conventional plasma doping method, an inner wall or the like of a chamber wherein the plasma doping is conducted, undergoes sputtering by the plasma, resulting in a drawback that atoms of the material of the chamber inner wall tend to deposit on the semiconductor substrate. When the inner wall of the plasma chamber is made of a stainless steel type material, Fe, Cr or the like tends to deposit on the semiconductor substrate. With an Al type material, not only Al but also Fe or the like contained in a small amount tend to deposit on the semiconductor substrate, and such elements are known to increase a leakage current of a source/drain junction.